1. Field of the Invention
The present invention relates to semiconductor memory devices and/or multi-port memory devices.
2. Description of the Related Art
A conventional dual port memory device includes a shared memory and input/output device in, for example, an integrated package. The conventional dual port memory device reads and/or writes data to a memory contained therein, for example, in response to a read and/or write signal.
FIG. 1 is a block diagram of an example conventional dual port memory device 100. Referring to FIG. 1, the dual port memory device 100 includes two interfaces 102 and 104, which are connected to external devices (not shown); and a controller 106, which controls signals input/output through the interfaces 102 and 104. The controller 106 reads data stored in a memory 108, and/or writes (stores) data in the memory 108. The data stored in the memory 108 may be output from the controller 106.
The interfaces 102 and 104 receive chip-enable signals CEL and CER, read/write signals R/WL and R/WR, address signals A0L through A13L (hereinafter, referred to as a first address signal) and, A0R through A13R (hereinafter, referred to as a second address signal) from external devices (not shown), respectively, and transfers these signals to the controller 106. The controller 106 analyzes the signals and reads and/or writes the analyzed results as data signals (D0L through D7L and/or D0R through D7R to and/or from the memory 108 under the control of the external devices. ‘L’ represents a left port of the dual port memory device 100, and ‘R’ represents a right port of the dual port memory device 100.
However, when the first address signal A0L through A13L and the second address signal A0R through A13R received from the external devices are the same, which indicates that the external devices have requested access to the same memory bank in the memory 108, an access collision may occur in the dual port memory device 100.